1. Field of the Invention
This invention generally relates to semiconductors, and more specifically, to patterned doping of semiconductor substrates using photosensitive monolayers. Embodiments of the invention, even more specifically, relate to such patterned doping of extremely thin semiconductor layers.
2. Background Art
In order to be able to make integrated circuits (ICs), such as memory, logic, photovoltaic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of semiconductors, such as complementary metal oxide semiconductors (CMOS) and photovoltaic devices. Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties. Additionally, all dimensions of the device must be scaled simultaneously in order to optimize the electrical performance of the device.
With conventional semiconductor scaling reaching fundamental limits, the semiconductor industry is looking at more unconventional and new approaches that will facilitate continued device performance improvements. As a result, attention has been given to using semiconductors with ultra or extremely thin silicon layers where the silicon or “device” layer has a thickness of from about seven nm and about ten nm.
Ultra thin semiconductor devices have very substantial advantages, however they also present difficult challenges. For instance, these devices can experience threshold-voltage and subthreshold slope fluctuation because of silicon thickness variations across the wafer. For example, a common silicon-on-insulator (SOI) device may have a silicon layer thickness of from 4-8 nm, with a variation in this thickness of 1 or more nm across the wafer.
Also, it has been determined that when conventional procedures are used to implant dopants into semiconductor layers that have a thickness of 10 nm or less, the ion implantation amorphizes the semiconductor layer. Recrystallizing the amorphous semiconductor layer is difficult, because of the limited amount of crystal seed layer that is available in semiconductor layers having a thickness of less than 10 nm that have been ion implanted into an amorphous crystal structure. The presence of an amorphous semiconductor material in a semiconductor device results in the semiconductor device having a high external resistance. Further, the resistance of the semiconductor device is increased by defects in the semiconductor layer that are produced by ion implantation. The ion implantation may also damage the gate dielectric.
As a result, conventional ion implantation procedures appear to be unsuitable for doping ultra thin semiconductor devices.